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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:00:13 12/01/2014 
-- Design Name: 
-- Module Name:    pc_adder - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; 

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pc_module is
    Port ( current_pc : out  STD_LOGIC_VECTOR (15 downto 0);
           branch_pc : in  STD_LOGIC_VECTOR (15 downto 0);
           branch_en : in  STD_LOGIC;
			  pause : in STD_LOGIC;
			  clk: in STD_LOGIC);
end pc_module;

architecture Behavioral of pc_module is
signal pc:STD_LOGIC_VECTOR(15 downto 0);
begin
	current_pc<=pc;
	
	process(pause,clk)
	begin
		if clk'event and clk = '1' then
			if pause = '0' then
				if branch_en='1' then
					pc<=branch_pc;
				elsif branch_en='0' then
					pc<=STD_LOGIC_VECTOR(unsigned(pc)+4);
				end if;
			end if;
		end if;
	end process;

end Behavioral;

